1. Field of the Invention
The present invention relates to a PLL circuit, and more specifically to a PLL circuit for generating clocks used as a time reference in a digital recording and reproducing device.
2. Description of the Related Art
A PLL circuit of the above kind is used for generating clocks used as a time reference when a data signal train having been recorded digitally is read for reproduction thereof. Specifically, in the case where the change point of the data signal train fluctuates in time and is not constant, an edge of the signal is detected to generate a pulse signal corresponding to the edge. By using a spectral component of a repeat frequency of the pulse signals, a continuous pulse signal can be generated. Hereinafter, this pulse signal is called a regenerated clock.
In general a PLL circuit is based on phase control. When a frequency of the data signal train which is a reference input to a phase comparator is too different from that of a regenerated clock which is a variable input, and the difference between these two frequencies is not in a frequency pull in range (frequency capture range), the control of a voltage controlled oscillator by the phase comparator is not carried out toward a reduction in the frequency difference, that is, a phase difference. As a result, phase locking is not achieved and an unlocked state remains. This problem is caused by a narrow capture range of the PLL circuit, and can be resolved by extending the capture range. Therefore, various methods have been proposed for extending the capture range, and one of them is described in Japanese Patent Laid-Open Publication No. Hei 4-215338. The PLL circuit described therein uses frequency control in addition to phase control in order to extend the capture range.
The conventional PLL circuit described above receives the data signal train in synchronization with a clock. In order to regenerate the data signal train, a regenerated clock synchronizing with both the phase and frequency of the clock is generated.
FIG. 1 is a block diagram showing the conventional PLL circuit. Phase comparator 101 compares phases between input data signal train ID and regenerated clock CK. When the phase of regenerated clock CK is ahead of that of input data signal train ID, phase comparator 101 outputs discharge control signal PDC at "1" level and charge control signal PC at "1" level if behind. Frequency comparator 102 compares frequencies between input data signal train ID and regenerated clock CK. When the frequency of regenerated clock CK is higher, frequency comparator 102 outputs discharge control signal FDC at "1" level and charge control signal FC at "1" level if lower. Control signal generating unit 103 generates discharge control signal DG and charge control signal CG in response to the supply of discharge control signals PDC and FDC, and charge control signals PC and FC respectively. Charge pump circuit 108 deposits or removes a charge in response to charge control signal CG or discharge control signal DG and generates charge pump signal VP of direct current. Low pass filter (hereinafter called LPF) 104 smoothes charge pump signal VP and outputs voltage control signal VC. Voltage controlled oscillator (hereinafter called VCO) 5 outputs oscillation signal OF whose frequency is controlled by voltage control signal VC. Frequency divider circuit 6 divides oscillation signal OF by a predetermined divide ratio and outputs regenerated clock CK at a desired frequency.
Charge pump circuit 108 comprises a P channel transistor and an N channel transistor. The source of the P channel transistor is connected to a power supply, and the P channel transistor receives the supply of charge control signal CG at its gate, and outputs charge pump signal VP from its drain. The source of the N channel transistor is connected to ground, and the N channel transistor receives the supply of discharge control signal DG at its gate. The drain of the N channel transistor is connected to that of the P channel transistor.
An operation of this PLL circuit will be explained next. When the frequency difference between the maximum repeat frequency of input data signal train ID and the frequency of regenerated clock CK is out of the capture range of the PLL circuit, frequency comparator 102 carries out the comparison between the above two frequencies. According to the difference of the frequency of regenerated clock CK to that of data signal train ID, discharge control signal FDC or charge control signal FC at level "1" is output. Control signal generating unit 103 outputs charge control signal CG or discharge control signal DG in response to charge control signal FC or discharge control signal FDC at "1" level. Charge pump circuit 108 deposits a charge and raises direct current charge pump signal VP when control signal CG is at level "0". When charge control signal DG is at level "1", charge pump circuit 108 removes a charge and lowers direct current charge pump signal VP and supplies VP to LPF 104. LPF 104 smoothes charge pump signal VP, outputs voltage control signal VC corresponding to the voltage of charge pump signal VP, and supplies the signal VC to VCO 5. VCO 5 outputs oscillation signal OF at a frequency proportional to control voltage VC. Frequency divider circuit 6 divides the frequency of oscillation signal OF by a predetermined divide ratio to output regenerated clock CK, and supplies CK to both frequency comparator 102 and phase comparator 101.
This operation is repeated until the frequency difference described above falls within the capture range and both charge control signal FC and discharge control signal FDC thus become level "0". When the frequency difference falls within the predetermined range through the above process, control signal generating unit 103 selects control signal PC or PDC from phase comparator 101, and outputs charge control signal CG or discharge control signal DG corresponding to the selected signal.
As has been described above, the difference between the maximum repeat frequency of data signal train ID and the frequency of regenerated clock CK is out of the capture range of the PLL circuit, frequency comparator 102 detects it and carries out a frequency pull in operation. When the frequency difference falls within the capture range, phase comparator 101 detects it and carries out a phase pull in operation and phase synchronizing operation. In this manner, the actual capture range can be extended.
However, as a first problem of this kind of conventional PLL circuit, although it is effective for a data signal train with almost constant frequencies, it is not applicable to widely changing frequencies such as in a constant angular velocity (CAV) operation of a compact disc.
This is because that only either the control signals FC and FDC (hereinafter called frequency error signals) of a frequency comparison result or control signals PC and PDC (hereinafter called phase error signals) of a phase comparison result are selected to drive the one charge pump circuit 8. As a result, the data signal train whose frequency and phase changes at the same time due to the CAV operation or the like cannot be followed and the phase locked state cannot be maintained. In other words, it is necessary to carry out the operation starting anew from frequency control at every frequency change. During this operation, the phase is unlocked and a stable phase locked state is not obtained.
A second problem is that extension of the range of the phase locked state, that is, extension of the lock range depends on the ability of phase control to follow a phase change, although the capture range can be extended. Therefore, the performance of the PLL circuit depends on the phase control operation alone.
This is because that the frequency control operation is not carried out in a phase locked state. In other words, a slight fluctuation in the frequency other than the large fluctuation in the frequency which occurs in the first problem is reflected as a phase error and the phase is locked by the phase control operation.
If the large and small fluctuations in the frequency is followed only by the phase control operation to maintain the locked state, a phase control loop having extremely large capture range and lock range is necessary. This circuit does not have any difference from a PLL circuit which basically has the phase control operation alone. In reality, a phase control operation having such large capture range and lock range is very difficult to be realized.
The third problem is that once the phase locked state is established, frequency control does not operate, even when the phase control and the frequency control cooperate in the PLL circuit at the same time by having charge pump circuits driven independently by the phase error signal and the frequency error signal, respectively, without switching between these signals in order to solve the first and the second problems.
This is because that a frequency error component is detected and fed back as a phase difference by the phase control system as long as it can follow. Therefore, once the phase locking is achieved, the frequency comparator does not sense unless the phase is unlocked.
In order to solve this problem, a frequency control system having sensitivity equivalent to that of the phase control system is necessary, and detection accuracy, that is, the resolution of the frequency comparator should be improved to a level equivalent to that of the phase comparator. As a result, such a frequency comparator means a frequency phase detector. When an input signal does not have constant change points thereof, like the case of a data signal train, a phase comparison result and a frequency comparison result may contradict. Therefore, phase comparison and frequency comparison cannot be applied at the same time.
In summary, since the above PLL circuit drives only one charge pump circuit by selecting either the frequency error signal or the phase error signal, data signal trains whose frequency is changing widely due to a CAV operation of a compact disc or the like and whose phase and frequency change at the same time cannot be followed and the phase locked state is not maintained. As a result, such a PLL circuit has a drawback that it is not applicable to a signal with widely changing frequency.
Furthermore, since the frequency control does not operate in the phase locked state and extension of the lock range depends on the ability of the phase control to follow phase changes although the capture range can be extended, it is a drawback of the PLL circuit that its performance is determined solely by the phase control operation.
Moreover, the frequency control does not operate once the phase locked state is established, since a frequency error component is detected and fed back as a phase error component as long as the phase control system can follow, even in the case where a PLL circuit is constructed so that the phase control and the frequency control may operate at the same time.